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| Genesys Logic, Inc. GL860A USB 2.0 UVC Camera Controller Datasheet Revision 1.00 May 09, 2007 GL860A USB 2.0 UVC Camera Controller Copyright: Copyright (c) 2007 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc. Disclaimer: ALL MATERIALS ARE PROVIDED "AS IS" WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE. Trademarks: is a registered trademark of Genesys Logic, Inc. All trademarks are the properties of their respective owners. Office: Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http://www.genesyslogic.com (c)2007 GenesysLogic, Inc. - All rights reserved. Page 2 GL860A USB 2.0 UVC Camera Controller Revision History Revision 0.9 0.91 1.00 Date 21/12/2006 01/03/2007 09/05/2007 First draft release Update register Add 46pin package information Description (c)2007 GenesysLogic, Inc. - All rights reserved. Page 3 GL860A USB 2.0 UVC Camera Controller TABLE OF CONTENTS CHAPTER 1 GENERAL DESCRIPTION ................................................... 7 CHAPTER 2 FEATURES .............................................................................. 8 CHAPTER 3 PIN ASSIGNMENT................................................................. 9 3.1 PINOUT ....................................................................................................... 9 3.2 PIN LIST.................................................................................................... 11 3.3 PIN DESCRIPTIONS ................................................................................... 12 CHAPTER 4 REGISTERS .......................................................................... 14 4.1 REGISTERS BASE ADDRESS...................................................................... 14 4.2 REGISTERS DESCRIPTIONS ...................................................................... 17 4.2.1 Global Control Register Part......................................................... 17 4.2.2 USB Register Part ........................................................................... 20 4.2.3 Sensor Register Part ....................................................................... 27 CHAPTER 5 FUNCTIONAL DESCRIPTION ......................................... 34 5.1 FUNCTION BLOCK .................................................................................... 34 5.2 OPERATION MODE................................................................................... 35 5.2.1 with Flash Memory ......................................................................... 35 5.2.2 without Flash Memory ................................................................... 35 CHAPTER 6 ELECTRICAL CHARACTERISTICS............................... 36 6.1 MAXIMUM RATINGS................................................................................. 36 6.2 DC CHARACTERISTICS ............................................................................ 36 CHAPTER 7 PACKAGE DIMENSION..................................................... 37 CHAPTER 8 ORDERING INFORMATION ............................................ 40 APPENDIX A. APPLICATION CIRCUIT................................................... 41 (c)2007 GenesysLogic, Inc. - All rights reserved. Page 4 GL860A USB 2.0 UVC Camera Controller LIST OF FIGURES FIGURE 3.1 - 48 PIN LQFN/LQFP PINOUT DIAGRAM ....................................................... 9 FIGURE 3.2 - 46 PIN LQFN PINOUT DIAGRAM ................................................................. 10 FIGURE 5.1 - BLOCK DIAGRAM ......................................................................................... 34 FIGURE 7.1 - GL860A 48 PIN LQFP PACKAGE................................................................ 37 FIGURE 7.2 - GL860A 48 PIN LQFN PACKAGE ............................................................... 38 FIGURE 7.3 - GL860A 46 PIN LQFN PACKAGE ............................................................... 39 (c)2007 GenesysLogic, Inc. - All rights reserved. Page 5 GL860A USB 2.0 UVC Camera Controller LIST OF TABLES TABLE 3.1 - 48-PIN LQFP/LQFN PIN LIST...................................................................... 11 TABLE 3.2 - 46-PIN LQFN PIN LIST.................................................................................. 12 TABLE 3.3 - 48-PIN LQFP/LQFN PIN DESCRIPTIONS ..................................................... 12 TABLE 3.4 - 46-PIN LQFN PIN DESCRIPTIONS ................................................................. 13 TABLE 4.1 - BASE ADDRESS FOR REGISTERS .................................................................... 14 TABLE 6.1 - MAXIMUM RATINGS ...................................................................................... 36 TABLE 6.2 - DC CHARACTERISTICS EXCEPT USB SIGNALS ............................................ 36 TABLE 8.1 - ORDERING INFORMATION ............................................................................. 40 (c)2007 GenesysLogic, Inc. - All rights reserved. Page 6 GL860A USB 2.0 UVC Camera Controller CHAPTER 1 GENERAL DESCRIPTION The GL860A is a high performance USB 2.0 Video class compliant controller for PC Camera and NB camera application. With the Genesys Logic's highly recognized self-developed USB high-speed transceiver, GL860A provides up to 30 fps at VGA or capture still images at 2 Mega pixels for fulfilling the mass bandwidth demand of video transferring. GL860A also support USB isochronous mode to provide certain bandwidth to insure user can get satisfied usage experience on video application even running high bandwidth consumption devices concurrently. The GL860A, compliant with Video Class 1.1 in USB Device Class (UVC), can be worked with Microsoft native driver. It makes you use USB PC Camera as you use an USB flash disk. Additionally, the GL860A provides an alternative proprietary driver to meet better image performance requirement. The GL860A integrates a highly flexible sensor interface to make it easily adopted with variety sensors in which include most popular CCD sensor module and CMOS sensors. The GL860A's low power consumption, low operation temperature characteristic also make it easy to implement a high quality PC Camera without worry about the noise signals of sensors to affect by high performance USB controller. (c)2007 GenesysLogic, Inc. - All rights reserved. Page 7 GL860A USB 2.0 UVC Camera Controller CHAPTER 2 FEATURES USB specification compliance - Complies with 480Mbps Universal Serial Bus specification rev. 2.0. - Complies with 12Mbps Universal Serial Bus specification rev. 2.0. - Support USB 2.0 Isochronous Video pipe to 24MB/s. Sensor interface - Programmable interface for popular general CCD module/CMOS sensor Non-process video streaming (USB High-speed connection) Support 4 USB endpoints - Endpoint 0: Control PIPE. - Endpoint 1: Isochronous/Bulk data in (configurable). - Endpoint 2: Interrupt OUT. - Endpoint 3: Interrupt IN. Embedded 8052 micro-controller - Operate @ 15 MHz clock. - 8K ROM. Support USB remote wakeup.. 3.3V/1.8V operation. 3.3V to 1.8V regulator is built-in. Capability to support on-line download program Available in 100-pin QFP and 48-pin LQFP package. Pass WHQL (Windows Hardware Quality Lab) Pass USB-IF (USB Implementers Forum) test Application Support OS USB Video Class V1.1 compliant The sensor, UVC, property control setting stored in external EEPROM (24Cxxx). (<= 8K bytes) Support alternative proprietary driver to enhance image performance. Non-UVC mode (Non-EEPROM), worked with proprietary driver Support YUV/RGB/I420 format Video stream up to12 fps in UXGA, 15 fps in SXGA, 30 fps in VGA UVC Class mode (External EEPROM), worked with OS native driver Support UVC uncompressed YUY2 format Video stream up to6 fps in UXGA, 9 fps in SXGA, 30 fps in VGA Still image captured up to UXGA (c)2007 GenesysLogic, Inc. - All rights reserved. NB Cam, PC Cam, UMPC, Game Console XP, Vista, MCE, XP64, Win2K Page 8 GL860A USB 2.0 UVC Camera Controller CHAPTER 3 3.1 Pinout PIN ASSIGNMENT Figure 3.1 - 48 Pin LQFN/LQFP Pinout Diagram (c)2007 GenesysLogic, Inc. - All rights reserved. Page 9 GL860A USB 2.0 UVC Camera Controller Figure 3.2 - 46 Pin LQFN Pinout Diagram (c)2007 GenesysLogic, Inc. - All rights reserved. Page 10 GL860A USB 2.0 UVC Camera Controller 3.2 Pin List Three type packages: Case 1 48 pin 8 bit sensor interface 12 GPIO pins LQFP/LQFN package Case 2 46 pin 8 bit sensor interface 12 GPIO pins LQFN package Table 3.1 - 48-Pin LQFP/LQFN Pin List Pin# 1 2 3 4 5 6 7 8 9 Pin Name DVDD CMS_DAT6 CMS_DAT7 CMS_DAT8 CMS_DAT9 GPIO0 GPIO1 GPIO2 GPIO3 Type Pin# P I I I I I/O I/O I/O I/O I/O P P Pin Name Type Pin# I I/O I/O P P P P I/O I/O P A P Pin Name Type Pin# P I I/O P I/O I/O I/O I/O I/O I/O I/O I Pin Name Type P P P P P I I I I I/O I/O P 13 HRST_ 14 GPIO13 15 GPIO14 16 VDD 17 DGND 18 AGND 19 AVDD 20 DM 21 DP 22 AGND 23 RREF 24 AVDD 25 DVDD 26 X1 27 X2 28 DGND 29 GPIO4 30 GPIO5 31 GPIO6 32 GPIO7 33 GPIO8 34 GPIO9 35 CMS_CLK 36 TEST 37 VDD 38 DGND 39 DVDD 40 VDD 41 DGND 42 CMS_DAT2 43 CMS_DAT3 44 CMS_DAT4 45 CMS_DAT5 46 VSYNC 47 HSYNC 48 DGND 10 CMS_DAT1 11 DGND 12 VDD (c)2007 GenesysLogic, Inc. - All rights reserved. Page 11 GL860A USB 2.0 UVC Camera Controller Table 3.2 - 46-Pin LQFN Pin List Pin# 1 2 3 4 5 6 7 8 9 Pin Name DVDD CMS_DAT6 CMS_DAT7 CMS_DAT8 CMS_DAT9 GPIO0 GPIO1 GPIO2 GPIO3 Type Pin# P I I I I I/O I/O I/O I/O I/O P P Pin Name Type Pin# I I/O I/O P P P P I/O I/O P A P Pin Name Type Pin# P I I/O P I/O I/O I/O I/O I/O I/O I/O I Pin Name Type P P P P I I I I I/O I/O 13 HRST_ 14 GPIO13 15 GPIO14 16 VDD 17 DGND 18 AGND 19 AVDD 20 DM 21 DP 22 AGND 23 RREF 24 AVDD 25 DVDD 26 X1 27 X2 28 DGND 29 GPIO4 30 GPIO5 31 GPIO6 32 GPIO7 33 GPIO8 34 GPIO9 35 CMS_CLK 36 TEST 37 VDD 38 DGND 39 DVDD 40 VDD 41 CMS_DAT2 42 CMS_DAT3 43 CMS_DAT4 44 CMS_DAT5 45 VSYNC 46 HSYNC 10 CMS_DAT1 11 DGND 12 VDD 3.3 Pin Descriptions Table 3.3 - 48-Pin LQFP/LQFN Pin Descriptions Pin Name VDD CMS_DAT1~9 GPIO0~9,13,14 Pin# 12,16,37,40 10,42~45,2~5 6~9,29~34, 14,15 Type P I I/O (pd) P P I (pu) P I/O I/O A I I/O I/O I (pd) I/O 1.8V power for crystal Sensor data bit 1~9 GPIO pins bit 0~9,13,14 Ground 3.3V core power Description GND DVDD HRST AVDD DM DP RREF X1 X2 CMS_CLK TEST VSYNC 11,17,18,22 28,38,41,48 1,25,39 13 19,24 20 21 23 26 27 35 36 46 Hardware reset, low active 3.3V analog power USB DUSB D Reference R 12M crystal in 12M crystal out Sensor clock Test mode Sensor Vsync (c)2007 GenesysLogic, Inc. - All rights reserved. Page 12 GL860A USB 2.0 UVC Camera Controller HSYNC NC 47 10 I/O Sensor Hsync No connection Table 3.4 - 46-Pin LQFN Pin Descriptions Pin Name VDD CMS_DAT1~9 GPIO0~9,13,14 Pin# 12,16,37,40 10,41~44,2~5 6~9,29~34, 14,15 Type P I I/O (pd) P P I (pu) P I/O I/O A I I/O I/O I (pd) I/O I/O 1.8V power for crystal Sensor data bit 1~9 GPIO pins bit 0~9,13,14 Ground 3.3V core power Description GND DVDD HRST AVDD33 DM DP RREF X1 X2 CMS_CLK TEST VSYNC HSYNC NC 11,17,18,22, 28,38 1,25,39 13 19,24 20 21 23 26 27 35 36 45 46 10 Hardware reset, low active 3.3V analog power USB DUSB D+ Reference R 12M crystal in 12M crystal out Sensor clock Test mode Sensor Vsync Sensor Hsync No connection Notation: Type O I B B/I B/O P A pu pd odpu Output Input Bi-directional Bi-directional, default input Bi-directional, default output Power / Ground Analog Internal pull up Internal pull down Open drain with internal pull up (c)2007 GenesysLogic, Inc. - All rights reserved. Page 13 GL860A USB 2.0 UVC Camera Controller CHAPTER 4 REGISTERS 4.1 Registers Base Address Table 4.1 - Base Address for Registers Mnemonic GP1_DAT GP1_INTPOL GP1_INTEN GP1_INT ROMFLG GP1_OE GP2_DAT GP2_INTPOL GP2_INTEN GP2_INTEN GP2_OE GCTL INT_MASK CLKCTL CPURST DEVCTL UEVT1 UEVT2 UEVT1EN UEVT2EN UTMCTL UTMDATL UTMDATH DEVADR MISC EPCTL1 EPCTL2 EPCTL3 EP0CTL RX0CNT FF0BUF FF1BUF Offset 00h 01h 02h 03h 04h 06h 07h 08h 09h 0Ah 0Dh 0Eh 0Fh 10h 11h 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h GPIO[7:0] data Interrupt polarity for GPIO[7:0] Interrupt enable for GPIO[7:0] Interrupt indication for GPIO[7:0] Reserved for internal use. Output enable for GPIO[7:0] GPIO[14:8] data Interrupt polarity for GPIO[14:8] Interrupt enable for GPIO[14:8] Interrupt indication for GPIO[14:8] Output enable for GPIO[14:8] Global control register Interrupt mask for each sub-module Sensor clock control CPU reset register USB Device control USB interrupt flag #1 USB interrupt flag #2 USB interrupt #1 enable USB interrupt #2 enable UTMI control UTMI data low byte UTMI data high byte USB device address Miscellaneous register Endpoint control 1 Endpoint control 2 Endpoint control 3 Endpoint 0 control Endpoint 0 receive length Endpoint 0 FIFO data Endpoint 1 FIFO data Description Default -8'h00 8'hFF 8'h00 8'hFF 8'h00 -8'h00 8'hFF 8'h00 8'h00 8'hFC 8'h00 8'h80 8'h00 8'h04 8'h00 8'h00 8'h00 8'h00 8'h0C --8'h00 8'h10 8'h00 8'h00 8'h00 8'h40 8'h00 8'h00 8'h00 (c)2007 GenesysLogic, Inc. - All rights reserved. Page 14 GL860A USB 2.0 UVC Camera Controller FF2BUF FF3BUF EP12CTL1 EP12CTL2 EP12CTL3 EP3CTL RX2CNT WAKEN HEADCTL1 HEADCTL2 HEAD0 HEAD1 SEN_CTL MCK_SAMP CLKRG_ CLKFG HV_CC RHNL RHNH_ FHNH FHNL RVPNL RVPNH_ RVLNH RVLNL FVPNL FVPNH_ FVLNH FVLNL MPNL MPNH_ MLNH MLNL SALNL SALNH_ EALNH EALNL SAPNL SAPNH_ EAPNH EAPNL SENINT 51h 52h 53h 54h 55h 56h 57h 5Fh 60h 61h 62h 63h C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h Endpoint 2 FIFO data Endpoint 3 FIFO data Endpoint1,2 control 1 Endpoint1,2 control 2 Endpoint1,2 control 3 Endpoint3 control Endpoint 2 receive length Wakeup source enable Head function control 1 Head function control 2 Head 0 data Head 1 data Sensor control Master clock selection / Select of sampling phase Falling/rising edge for MCLK Clock counter for Hsync/Vsync output Pixel number for rising edge of Hsync output Pixel number for rising/falling of Hsync output Pixel number for falling edge of Hsync output Pixel number for rising edge of Vsync output Pixel number for rising/falling of Vsync output Pixel number for falling edge of Vsync output Line number for rising edge of Vsync output Line number for rising/falling of Vsync output Line number for falling edge of Vsync output Maximum pixel number Maximum pixel/line number Maximum line number Start line number of active window Start/end line number of active window End line number of active window Start pixel number of active window Start/end pixel number of active window End pixel number of active window Sensor interrupt 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h03 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 (c)2007 GenesysLogic, Inc. - All rights reserved. Page 15 GL860A USB 2.0 UVC Camera Controller SENINT_EN SUB_SAMP Notation: R/W R/O W/O R/W1C R/W/C D7h D8h Sensor interrupt enable Sub-sampling mode 8'h00 8'h00 Read / Write Read Only Write Only Read / Write "1" to Clear Read / Write and hardware automatic Clear (c)2007 GenesysLogic, Inc. - All rights reserved. Page 16 GL860A USB 2.0 UVC Camera Controller 4.2 Registers Descriptions 4.2.1 Global Control Register Part Offset 00h - GP1_DAT GPIO7 R/W 7-0 GPIO[7:0] GPIO6 R/W GPIO5 R/W GPIO4 R/W GPIO3 R/W GPIO2 R/W GPIO1 R/W GPIO0 R/W GPIO7~0 data. 0 GPIO7~0O write. 1 GPIO7~0I read. Offset 01h - GP1_INTPOL .............................................................. Default value = 8'h00 GPIO7 R/W 7-0 GPIO[7:0] GPIO6 R/W GPIO5 R/W GPIO4 R/W GPIO3 R/W GPIO2 R/W GPIO1 R/W GPIO0 R/W GPIO7~0 interrupt polarity. 0 H2L 1 L2H Offset 02h - GP1_INTEN .............................................................. Default value = 8'hFF GPIO7 R/W 7-0 GPIO[7:0] GPIO6 R/W 0 1 GPIO5 R/W Unmask int Mask int GPIO4 R/W GPIO3 R/W GPIO2 R/W GPIO1 R/W GPIO0 R/W Offset 03h - GP1_INT .................................................................. Default value = 8'h00 GPIO7 W1C 7-0 GPIO[7:0] GPIO6 W1C GPIO5 W1C GPIO4 W1C GPIO3 W1C GPIO2 W1C GPIO1 W1C GPIO0 W1C GPIO7~0 interrupt indication. Offset 04h - ROMFLG ................................................................. Default value = 8'hFF ROMFLG7 ROMFLG6 ROMFLG5 ROMFLG4 ROMFLG3 ROMFLG2 ROMFLG1 ROMFLG0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 ROMFLG[7:0] Reserved for internal use. (c)2007 GenesysLogic, Inc. - All rights reserved. Page 17 GL860A USB 2.0 UVC Camera Controller Offset 06h - GP1_OE .................................................................... Default value = 8'h00 GPIO7 R/W 7-0 GPIO[7:0] GPIO6 R/W GPIO5 R/W GPIO7~0 control. 0 Input 1 Output GPIO4 R/W GPIO3 R/W GPIO2 R/W GPIO1 R/W GPIO0 R/W Offset 07h - GP2_DAT --GPIO14 R/W GPIO13 R/W GPIO12 R/W GPIO11 R/W GPIO10 R/W GPIO9 R/W GPIO8 R/W 7 RESERVED 6-0 GPIO[14:8] GPIO14~8 data. 0 GPIO14~8O write. 1 GPIO14~8I read. Offset 08h - GP2_INTPOL .............................................................. Default value = 8'h00 --GPIO14 R/W GPIO13 R/W EAPN11 R/W SAPN11 R/W GPIO10 R/W GPIO9 R/W GPIO8 R/W 7 RESERVED 6-5 GPIO[14:13] GPIO14~13 interrupt polarity. 0 H2L 1 L2H 4 3 EAPN11 Pixel number of end active window Pixel number of start active window GPIO10~8 interrupt polarity. 0 H2L 1 L2H SAPN11 2-0 GPIO[10:8] Offset 09h - GP2_INTEN .............................................................. Default value = 8'hFF --GPIO14 R/W - GPIO13 R/W GPIO12 R/W GPIO11 R/W GPIO10 R/W GPIO9 R/W GPIO8 R/W 7 RESERVED 6-0 GPIO[14:8] 0 1 Unmask int Mask int Offset 0Ah - GP2_INT .................................................................. Default value = 8'h00 --GPIO14 W1C GPIO13 W1C GPIO12 W1C GPIO11 W1C GPIO10 W1C GPIO9 W1C GPIO8 W1C (c)2007 GenesysLogic, Inc. - All rights reserved. Page 18 GL860A USB 2.0 UVC Camera Controller 7 RESERVED 6-0 GPIO[14:8] - GPIO14~8 interrupt indication. Offset 0Dh - GP2_OE .................................................................... Default value = 8'h00 --GPIO14 R/W GPIO13 R/W GPIO14~8 control. 0 Input 1 Output GPIO12 R/W GPIO11 R/W GPIO10 R/W GPIO9 R/W GPIO8 R/W 7 RESERVED 6-0 GPIO[14:8] Offset 0Eh - GCTL ....................................................................... Default value = 8'hFC --7-3 RESERVED 2 SEN_EN --------SEN_EN R/W --SEN_CLKEN R/W 1 RESERVED 0 SEN_CLKEN Register enable to sensor interface. 0 Default/Reset state 1 Enable 0 Stop clock to sensor interface 1 Enable clock to sensor interface Offset 0Fh - INT_MASK ................................................................. Default value = 8'h00 ----------PIE_INTM ASK R/W --SEN_INTM ASK R/W 7-3 RESERVED 2 PIE_INTMASK 0 Mask of SIE_INT 1 Unmask of SIE_INT 1 RESERVED 0 SEN_INTMASK 0 Mask of SEN_INT 1 Unmask of SEN_INT Offset 10h - CLKCTL .................................................................... Default value = 8'h80 ----SEN_CLKC SEN_CLKC SEN_CLKC SEN_CLKC SEN_CLKC TL4 TL3 TL2 TL1 TL0 R/W R/W R/W R/W R/W 7-6 RESERVED 4 SEN_CLKCTL4 Operating clock of sensor interface is 48M (c)2007 GenesysLogic, Inc. - All rights reserved. Page 19 GL860A USB 2.0 UVC Camera Controller 3 2 1 0 SEN_CLKCTL3 Operating clock of sensor interface is 7.5M SEN_CLKCTL2 Operating clock of sensor interface is 15M SEN_CLKCTL1 Operating clock of sensor interface is 30M SEN_CLKCTL0 Operating clock of sensor interface is 60M Offset 11h - CPURST ................................................................... Default value = 8'h00 -------------CPU2SEN_ RST -- R/W 7-1 RESERVED 0 CPU2SEN_RST 0 Unreset 1 Reset SEN_TOP 4.2.2 USB Register Part Offset 40h - DEVCTL1 ................................................................. Default value = 8'h04 HS_SUSPD CHIRP_DEN TSTPKEN TSTPKRST R/W/C R/W R/W/C High Speed Suspend This bit can be set/cleared by uC. When chip is in high speed mode and suspends --- DISGLUSB DIS_SUS R/W R/W PWRDN R/W/C W/O 7 HS_SUSPD 6 CHIRP_DEN 5 TSTPKEN 4 TSTPKRST 3 RESERVED 2 DISGLUSB 1 DIS_SUS 0 PWRDN event is detected, uC can set HS_SUS and PWRDN bits to enter suspend mode. This bit will be cleared automatically when end of resume signaling (K to SE0) is detected. Set this bit will enable HS-KJKJKJ chirp detection. After correct HS chirp sequence is detected, CHIRP_DET bit in USBEVT1 will be set. Enable Endpoint 1 data packet transmission without receiving IN token. This bit is cleared by hardware when TSTPKTX interrupt is set. Reset Read Pointer of TX FIFO0. Note: Write pointer & FIFO data keep unchanged. When this bit is set to `1', D+ pin will be left floating so that no connect will be detected on the host side. Disable suspend detection Power down mode If USB suspend is detected, firmware can set PWRDN to put the controller into power down mode. Power down mode stops oscillator and freezes at known states, and no more command can be executed. Hardware will automatically clear PWRDN upon hardware reset or interrupted event. Offset 41h - UEVT1 ....................................................................... Default value = 8'h00 SOF R/W1C CHIRP_DET URST R/W1C WAKEUP R/W1C RESUME R/W1C SUSPD R/W1C EP0TX R/W1C EP0RX R/W1C R/W1C (c)2007 GenesysLogic, Inc. - All rights reserved. Page 20 GL860A USB 2.0 UVC Camera Controller 7 SOF 6 CHIRP_DET 5 SRST 4 3 2 1 0 WAKEUP RESUME SUSPD EP0TX EP0RX SOF token packet received event Chirp sequence "K-J-K-J-K-J" detected. USB Reset (SE0 for 3ms) is detected. After receiving this event, uC should begin the HS detection handshake. Remote-wakeup event is detected during suspend state USB resume detected USB suspend detected Endpoint 0 transmits a data packet completely. Endpoint 0 receives a data packet. Offset 42h - UEVT2 ....................................................................... Default value = 8'h00 SETUP R/W1C 7 6 5-3 2 1 0 TSTPKTX R/W1C EP2NAK R/W1C EP1NAK R/W1C EP0NAK R/W1C EP3TX R/W1C EP2RX R/W1C EP1TX R/W1C SETUP TSTPKTX EPnNAK EP3TX EP2RX EP1TX Device received a setup packet. Test Packet is sent complete. Endpoint receiving or transmitting NAK flag. (n=2~0) Endpoint 3 transmission done event Endpoint 2 receive done event. Endpoint 1 transmission done event. Offset 43h - UEVT1EN ................................................................. Default value = 8'h00 SOFEN R/W 7-0 CHIRPDEN URSTEN R/W R/W WKUPEN R/W RSMEN R/W SUSEN R/W EP0TXEN EP0RXEN R/W R/W These are the interrupt enable bits for USB event interrupt #1 to uC. (Mask bits of USBEVT1) Offset 44h - UEVT2EN ................................................................. Default value = 8'h00 SETUPEN TSTPKTXEN EP2NAKEN EP1NAKEN EP0NAKEN EP3TXEN EP2RXEN EP1TXEN R/W 7-0 R/W R/W R/W R/W R/W R/W R/W These are the interrupt enable bits for USB event interrupt #2 to uC. (Mask bits of USBEVT1) Offset 45h - UTMCTL ................................................................. Default value = 8'h0C VMI R/O Write Read VPI R/O OPMOD1 R/W OPMOD0 R/W FSPEED R/W HSTERM R/W TXVLDH/ RXVLDH TXVLD/ RXACTV R/W R/W To generate HS Chirp, set to 8'b0010_0111. To generate FS Remote-Wake-Up, set to 8'b0010_1111. RXACTV/RXVLDH will reflect the real-time status of the UTM interface. (c)2007 GenesysLogic, Inc. - All rights reserved. Page 21 GL860A USB 2.0 UVC Camera Controller Offset 46h - UTMDATL UTMD7 R/W UTMD6 R/W UTMD5 R/W UTMD4 R/W UTMD3 R/W UTMD2 R/W UTMD1 R/W UTMD0 R/W Offset 47h - UTMDATH UTMD15 R/W UTMD14 R/W UTMD13 R/W UTMD12 R/W UTMD11 R/W UTMD10 R/W UTMD9 R/W UTMD8 R/W UTMDATL/UTMDATH are used to set/read data to/from UTM interface. Write Set the output data on UTM interface. To issue chirp or remote-wake-up, these 2 registers should set to 4'h0000. Read Reflect the real-time status of the UTM data bus. Offset 48h - DEVADR ................................................................... Default value = 8'h00 --DEVADR6 DEVADR5 DEVADR4 DEVADR3 DEVADR2 DEVADR1 DEVADR0 R/W R/W R/W R/W R/W R/W R/W 7 RESERVED 6-0 This register is used to store USB device address. Offset 49h - MISC ........................................................................ Default value = 8'h00 SUSPD R/O 7 6 5 4 3-2 1 ADDR R/O DEFAULT R/O POWER R/O ----SF R/W SUS_DIS R/W SUSPD ADDR DEFAULT POWER RESERVED SF 0 SUS_DIS Device is in the suspend state. Device is in the address state. Device is in the default state. Device is in the powered state. Short frame mode, using in suspend detection. 0 Normal mode, needs 3ms bus idle to enter suspend mode 1 Short frame mode, needs only 200us to enter suspend mode Disable suspend detection. Offset 4Ah - EPCTL1 ..................................................................... Default value = 8'h00 EP1ISOEN DISNYET R/W 7 EP1ISOEN 6 DISNYET 5 TATODEN 4 EP0TEST R/W TATODEN EP0TEST BULK_RST R/W R/W R/W EP3EN R/W EP2EN R/W EP1EN R/W 0 Endpoint 1 is BULK IN mode. 1 Endpoint 1 is ISO IN mode. Disable USB NYET response, instead of ACK response. Turn around time out detect enable. 0 Normal mode, Endpoint 0 doesn't response to bulk IN/OUT packet. Page 22 (c)2007 GenesysLogic, Inc. - All rights reserved. GL860A USB 2.0 UVC Camera Controller 1 Test mode, Endpoint 0 can response all packet. EP1 bulk mode initial reset Endpoint 1, 2, 3 TX/RX enable. (n=3~1) After device is configured, EPTX1EN, EPTX2EN,EP3TXEN, EPRX1EN, EPRX2EN,EP3RXEN write 1 to decide Endpoint 1,2,3 IN or OUT. Before endpoint is enabled, it won't response to any USB transaction. 3 BULK_RST 2-0 EPnEN Offset 4Bh - EPCTL2 ..................................................................... Default value = 8'h00 --7 6-4 3 2-0 EP3TGRST EP2TGRST EP1TGRST W/O W/O W/O --EP3STL R/W EP2STL R/W EP1STL R/W RESERVED EPnTGRST RESERVED EPnSTL Endpoint toggle reset. (n=3~1) Endpoint stall. (n=3~1) Offset 4Ch - EPCTL3 ..................................................................... Default value = 8'h00 EP3TOG R/O 7-5 4 3 2 1 0 EP2TOG R/O EP1TOG R/O TX3FFPOP R/W FF3RST R/W RX0FFPSH TX0FFPOP R/W R/W FF0RST R/W EPnTOG TX3FFPOP FF3RST RX0FFPSH TX0FFPOP FF0RST Toggle indication of DATA packet. (n=3~1) uC pop endpoint 3 TXFIFO enable. Reset endpoint 3 FIFO read/write pointer. Data in FIFO remain unchanged. uC push endpoint 0 RXFIFO enable uC pop endpoint 0 TXFIFO enable. Reset endpoint 0 TXFIFO read/write pointer. Data in FIFO remain unchanged. Offset 4Dh - EPCTL3 ..................................................................... Default value = 8'h00 RX0DIS R/W 7 RX0DIS RXSETUP R/O RXOUT R/O RXSEQ R/W EP0RXSTL EP0TXSTL R/W R/W TX0OE R/W/C TX0SEQ R/W Disable receiving capability on endpoint 0 Upon successfully receiving a data packet on endpoint 0, hardware will automatically 6 RXSETUP 5 RXOUT 4 RXSEQ 3 EP0RXSTL set this bit to `1'. At this time, no more OUT data on endpoint 0 can be accepted, hardware will respond with NAK. Note, for SETUP transaction, hardware will always accept and respond with ACK. 0 Endp0 FIFO is available for data receiving. 1 Endp0 FIFO is not available Endpoint 0 received token is SETUP. Endpoint 0 received token is OUT. Endpoint 0 received data toggle. 0 The received data is DATA0 1 The received data is DATA1 Endpoint 0 receiving stall. Endpoint 0 will respond with a STALL to a valid OUT transaction. This bit will Page 23 (c)2007 GenesysLogic, Inc. - All rights reserved. GL860A USB 2.0 UVC Camera Controller be cleared by SETUP transaction automatically. Endpoint 0 transmitting stall. Endpoint 0 will respond with a STALL to a valid IN transaction. This bit will be cleared by SETUP transaction automatically. Ready to transmit control data. Endpoint 0 transmission data toggle. 0 TX DATA0 1 TX DATA1 2 EP0TXSTL 1 TX0OE 0 TX0SEQ Offset 4Eh - RX0CNT .................................................................... Default value = 8'h00 CTLRD R/W 7 CTLRD RX0CNT6 RX0CNT5 RX0CNT4 RX0CNT3 RX0CNT2 RX0CNT1 RX0CNT0 R/O R/O R/O R/O R/O R/O R/O 6-0 RX0CNT[6:0] Control pipe(Endpoint 0) control to prevent response of bulk packet. 0 Host send OUT packet right after SETUP package. (Has a IN packet status) 1 Host send IN packet right after SETUP package. (Has a OUT packet status) The received DATA length of endpoint 0. Offset 4Fh - FF0BUF .................................................................... Default value = 8'h00 FF0DAT7 R/W FF0DAT6 R/W FF0DAT5 R/W FF0DAT4 R/W FF0DAT3 R/W FF0DAT2 R/W FF0DAT1 R/W FF0DAT0 R/W 7-0 FF0DAT[7:0] Data entry for endpoint 0 FIFO. Writing this register will push data into endpoint 0 TXFIFO, and reading will pop data from endpoint 0 RXFIFO. Offset 50h - FF1BUF .................................................................... Default value = 8'h00 FF1DAT7 R/W FF1DAT6 R/W FF1DAT5 R/W FF1DAT4 R/W FF1DAT3 R/W FF1DAT2 R/W FF1DAT1 R/W FF1DAT0 R/W 7-0 FF1DAT[7:0] Data entry for endpoint 1 FIFO. Writing this register will push data into endpoint 1 TXFIFO, and reading will pop data from endpoint 1 RXFIFO. Offset 51h - FF2BUF .................................................................... Default value = 8'h00 FF2DAT7 R/W FF2DAT6 R/W FF2DAT5 R/W FF2DAT4 R/W FF2DAT3 R/W FF2DAT2 R/W FF2DAT1 R/W FF2DAT0 R/W 7-0 FF2DAT[7:0] Data entry for endpoint 2 FIFO. Writing this register will push data into endpoint 2 TXFIFO, and reading will pop data from endpoint 2 RXFIFO. (c)2007 GenesysLogic, Inc. - All rights reserved. Page 24 GL860A USB 2.0 UVC Camera Controller Offset 52h - FF3BUF .................................................................... Default value = 8'h00 FF3DAT7 R/W FF3DAT6 R/W FF3DAT5 R/W FF3DAT4 R/W FF3DAT3 R/W FF3DAT2 R/W FF3DAT1 R/W FF3DAT0 R/W 7-0 FF3DAT[7:0] Data entry for endpoint 3 FIFO. Writing this register will push data into endpoint 3 TXFIFO, and reading will pop data from endpoint 3 RXFIFO. Offset 53h - EP12CTL1 ................................................................. Default value = 8'h00 --------TXASEL2 R/W TXASEL1 R/W TXASEL0 R/W -- -- 7-3 RESERVED 2-0 TXASEL[2:0] 001 TXAFFSEL1 set 1 010 TXAFFSEL2 set 1 011 TXAFFSEL3 set 1 100 TXAFFSEL4 set 1 101 TXAFFSEL5 set 1 110 TXAFFSEL0 set 1 In normal operation, bulk FIFO is pushed/popped by DTV/SEN engine or USB SIE engine. But use the register, we can push/pop bulk FIFO by uC. uC accessing ISO/Bulk IN FIFO: Set TXFFPSH=1, and use TXAFFSEL to select DATA A FIFO, or use TXBFFSEL to select DATA B FIFO. Then write data to FF1BUF to begin pushing FIFO. To pop data from FIFO, just set TXFFPSH = 0, set TXBFFSEL or TXAFFSEL to select DATA A/DATA B FIFO, and read data from FF1BUF to begin popping FIFO. After pop/push is complete, uC must clear all FIFO select and control setting on FFCTL. Offset 54h - EP12CTL2 .................................................................. Default value = 8'h00 --7-6 5 4 3 2 1 0 RESERVED DTXEN TXFMOD TXFFRST RXFFRST TXFFPSH RXFFPSH --DTXEN R/W TXFMOD R/W TXFFRST R/W RXFFRST R/W TXFFPSH R/W RXFFPSH R/W Firmware set ENDP1 TX mode. Firmware test EP1 FIFO, read/write byte mode. Reset TXFIFO, cleared by hardware itself. Reset RXFIFO, cleared by hardware itself. Push indication for TX FIFO Push indication for RX FIFO Offset 55h - EP12CTL2 .................................................................. Default value = 8'h00 ANK1_EN R/W 7 ANK1_EN --------ANAKEP2 R/W EP2NAK R/W EP1NAK R/W Force NAK of endpoint 1. Page 25 (c)2007 GenesysLogic, Inc. - All rights reserved. GL860A USB 2.0 UVC Camera Controller 6-3 RESERVED 2 ANAKEP2 1 EP2NAL 0 EP1NAK Automatic NAK of endpoint 2, after receiving a data packet. (Bit FNAKEP2 would be set to 1, after receiving a data packet.). Force NAK of endpoint 2. Force NAK of endpoint 1. Offset 56h - EP3CTL ...................................................................... Default value = 8'h00 TXOE3 R/W/C TX3CNT6 R/O TX3CNT5 R/O TX3CNT4 R/O TX3CNT3 R/O TX3CNT2 R/O TX3CNT1 R/O TX3CNT0 R/O 7 TXOE3 6-0 TX3CNT[6:0] Ready to transmit endpoint 3 data The transmit DATA length of endpoint 3 Offset 57h - RX2CNT ................................................................... Default value = 8'h00 RX2DIS R/W 7 RX2DIS RX2CNT6 RX2CNT5 RX2CNT4 RX2CNT3 RX2CNT2 RX2CNT1 RX2CNT0 R/O R/O R/O R/O R/O R/O R/O Disable receiving capability on endpoint 2 Upon successfully receiving a data packet on endpoint 2, hardware will automatically set this bit to `1'. At this time, no more OUT data on endpoint 2 can be accepted, hardware 6-0 RX2CNT[6:0] will respond with NAK. 0 Endp2 FIFO is available for data receiving. 1 Endp2 FIFO is not available The received DATA length of endpoint 2 Offset 5Fh - WAKEN .................................................................... Default value = 8'h00 --RAMDIS3 RAMDIS2 RAMDIS1 R/W R/W R/W --GP4EN R/W GP3EN R/W GP2EN R/W 7 6 5 4 3 2 1 0 Enable falling edge event on corresponding pins as remote wakeup source. RESERVED RAMDIS3 Endp3 RAM disable. RAMDIS2 Endp2 RAM disable. RAMDIS1 Endp1 RAM disable. RESERVED GP4EN Falling edge event on GPIO4 wakeup enable. GP3EN Falling edge event on GPIO3 wakeup enable. GP2EN Falling edge event on GPIO2 wakeup enable Offset 60h - HEADCTL1 ................................................................. Default value = 8'h00 ------------FRAM_EN HEAD_EN R/W R/W (c)2007 GenesysLogic, Inc. - All rights reserved. Page 26 GL860A USB 2.0 UVC Camera Controller 7-2 RESERVED 1 FRAM_EN 0 HEAD_EN Set 1 to enable, header function.. Set 1 to add Header for each frame, Set 0 to add Header for each SOF. Offset 61h - HEADCTL2 ................................................................. Default value = 8'h00 --------HEADCNT0 HEADCNT0 HEADCNT0 HEADCNT0 R/W R/W R/W R/W 7-4 RESERVED 3-0 HEADCNT[3:0] Select header byte count from 0~8. Offset 62h - HEAD0 ....................................................................... Default value = 8'h00 H0DAT7 R/W H0DAT6 R/W H0DAT5 R/W Head data 0. H0DAT4 R/W H0DAT3 R/W H0DAT2 R/W H0DAT1 R/W H0DAT0 R/W 7-0 H0DAT[7:0] Offset 63h - HEAD1 ....................................................................... Default value = 8'h00 H1DAT7 R/W H1DAT6 R/W H1DAT5 R/W Head data 1. H1DAT4 R/W H1DAT3 R/W H1DAT2 R/W H1DAT1 R/W H1DAT0 R/W 7-0 H1DAT[7:0] 4.2.3 Sensor Register Part Offset C0h - SENCTL ................................................................... Default value = 8'h00 INCTST R/W 7 INCTST 6 EDGESEL EDGESEL R/W CLKOE R/W VSATV R/W HSATV R/W HVOE R/W --BITMODE R/W 5 CLKOE 4 VSATV 3 HSATV 2 HVOE 0 No incremental data on CMSDAT[9:0] 1 Incremental data on CMSDAT[9:0] for debugging Rising/Falling edge of PIX_CLK selection 0 The same with the PIX_CLK 1 Inverse with the PIX_CLK MAS_CLK output selection 0 Input clock (PIX_CLK) 1 Output clock (MAS_CLK) Select of timing to reset internal line count when VSYNC is coming from sensor. 0 Falling edge 1 Rising edge Select of timing to reset internal pixel count when HSYNC is coming from sensor. 0 Falling edge 1 Rising edge HSYNC/VSYNC output enable Page 27 (c)2007 GenesysLogic, Inc. - All rights reserved. GL860A USB 2.0 UVC Camera Controller 0 Output 1 Input Pixel data bit number. 0 8bit pixel date 1 10bit pixel date (In this mode, 10 bit data will be transferred to USB by continuous two byte. The first byte is MSB 8 bit, and the next byte is LSB2 bit and 6'b0.) 1 RESERVED 0 BITMODE Offset C1h - MCK_SAMP ............................................................... Default value = 8'h03 SAMP4 R/W 7-3 SAMP[4:0] 2-0 MCK[2:0] SAMP3 R/W SAMP2 R/W SAMP1 R/W SAMP0 R/W MCK2 R/W MCK1 R/W MCK0 R/W Sampling phase of data bus. Selection of master clock to sensor (MCLK) 000 MCLK is 60MHz 001 MCLK is 30MHz 010 MCLK is 20MHz 011 MCLK is 15MHz 100 MCLK is 12MHz 101 MCLK is 10MHz 110 MCLK is 8.57MHz 111 MCLK is 7.5MHz Address Data 0x10 0x01 0xC1 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 CLOCK 60MHz 30 20 15 12 10 8.57 7.5 CLOCK 30MHz 15 10 7.5 6 5 Page 28 Address Data 0x10 0x02 0xC1 0x00 0x01 0x02 0x03 0x04 0x05 (c)2007 GenesysLogic, Inc. - All rights reserved. GL860A USB 2.0 UVC Camera Controller 0x06 0x07 Address Data 0x10 0x04 0xC1 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Address Data 0x10 0x08 0xC1 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Address Data 0x10 0x10 0xC1 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 4.2857 3.75 CLOCK 15MHz 7.5 5 3.75 3 2.5 2.1429 1.875 CLOCK 7.5MHz 3.75 2.5 1.875 1.5 1.25 1.0714 0.9375 CLOCK 48MHz 24 16 12 9.6 8 6.8571 6 (c)2007 GenesysLogic, Inc. - All rights reserved. Page 29 GL860A USB 2.0 UVC Camera Controller Offset C2h - CLKRG_CLK ........................................................... Default value = 8'h00 ----CLKFG2 R/W CLKFG1 R/W CLKFG0 R/W CLKRG2 R/W CLKRG1 R/W CLKRG0 R/W 5-3 CLKFG[2:0] 2-0 CLKRG[2:0] Falling edge of MCLK. Rising edge of MCLK. Offset C3h - HV_CC .................................................................... Default value = 8'h00 ----VCC2 R/W VCC1 R/W VCC0 R/W HCC2 R/W HCC1 R/W HCC0 R/W 5-3 VCC[2:0] 2-0 HCC[2:0] Phase of output VSYNC. Phase of output HSYNC. Offset C4h - RHNL ...................................................................... Default value = 8'h00 RHN7 R/W RHN6 R/W RHN5 R/W RHN4 R/W RHN3 R/W RHN2 R/W RHN1 R/W RHN0 R/W Offset C5h - RHNH_FHNH ............................................................ Default value = 8'h00 --RHN[10:0] --FHN10 R/W FHN9 R/W FHN8 R/W RHN10 R/W RHN9 R/W RHN8 R/W Pixel number of the rising edge of HSYNC Offset C6h - FHNL ....................................................................... Default value = 8'h00 FHN7 R/W FHN[10:0] FHN6 R/W FHN5 R/W FHN4 R/W FHN3 R/W FHN2 R/W FHN1 R/W FHN0 R/W Pixel number of falling edge of HSYNC Offset C7h - RVPNL ...................................................................... Default value = 8'h00 RVPN7 R/W RVPN6 R/W RVPN5 R/W RVPN4 R/W RVPN3 R/W RVPN2 R/W RVPN1 R/W RVPN0 R/W (c)2007 GenesysLogic, Inc. - All rights reserved. Page 30 GL860A USB 2.0 UVC Camera Controller Offset C8h - RVPNH_RVI ............................................................ Default value = 8'h00 --RVPN[10:0] --RVLN10 R/W RVLN9 R/W RVLN8 R/W RVPN10 R/W RVPN9 R/W RVPN8 R/W Number of the rising pixel number Offset C9h - RVLNL ...................................................................... Default value = 8'h00 RVLN7 R/W RVLN[10:0] RVLN6 R/W RVLN5 R/W RVLN4 R/W RVLN3 R/W RVLN2 R/W RVLN1 R/W RVLN0 R/W Line number for Rising edge of VSYNC line number Offset CAh - FVPNL ...................................................................... Default value = 8'h00 FVPN7 R/W FVPN6 R/W FVPN5 R/W FVPN4 R/W FVPN3 R/W FVPN2 R/W FVPN1 R/W FVPN0 R/W Offset CBh - FVPNH_FVLNH ......................................................... Default value = 8'h00 --FVPN[10:0] --FVLN10 R/W FVLN9 R/W FVLN8 R/W FVPN10 R/W FVPN9 R/W FVPN8 R/W Pixel number for falling edge of VSYNC Offset CCh - FVLNL ...................................................................... Default value = 8'h00 FVLN7 R/W FVLN[7:0] FVLN6 R/W FVLN5 R/W FVLN4 R/W FVLN3 R/W FVLN2 R/W FVLN1 R/W FVLN0 R/W Line number for falling edge of VSYNC Offset CDh - MPNL ...................................................................... Default value = 8'h00 MPN7 R/W MPN6 R/W MPN5 R/W MPN4 R/W MPN3 R/W MPN2 R/W MPN1 R/W MPN0 R/W Offset CEh - MPNH_MLNH ........................................................... Default value = 8'h00 --MPN[10:0] MLN[10:0] --MLN10 R/W MLN9 R/W MLN8 R/W MPN10 R/W MPN9 R/W MPN8 R/W Pixel number for maximum window Line number for maximum window Page 31 (c)2007 GenesysLogic, Inc. - All rights reserved. GL860A USB 2.0 UVC Camera Controller Offset CFh - MLNL ....................................................................... Default value = 8'h00 MLN7 R/W MLN6 R/W MLN5 R/W MLN4 R/W MLN3 R/W MLN2 R/W MLN1 R/W MLN0 R/W Offset D0h - SALNL ....................................................................... Default value = 8'h00 SALN7 R/W SALN[10:0] EALN[10:0] SALN6 R/W SALN5 R/W SALN4 R/W SALN3 R/W SALN2 R/W SALN1 R/W SALN0 R/W Line number of start active window Line number of end active window Offset D1h - SALNH_EALNH .......................................................... Default value = 8'h00 ----EALN10 R/W EALN9 R/W EALN8 R/W SALN10 R/W SALN9 R/W SALN8 R/W Offset D2h - EALNL ...................................................................... Default value = 8'h00 EALN7 R/W EALN6 R/W EALN5 R/W EALN4 R/W EALN3 R/W EALN2 R/W EALN1 R/W EALN0 R/W Offset D3h - SAPNL ...................................................................... Default value = 8'h00 SAPN7 R/W SAPN[10:0] EAPN[10:0] SAPN6 R/W SAPN5 R/W SAPN4 R/W SAPN3 R/W SAPN2 R/W SAPN1 R/W SAPN0 R/W Pixel number of start active window Pixel number of end active window Offset D4h - SAPNH_EAPNH .......................................................... Default value = 8'h00 ----EAPN10 R/W EAPN9 R/W EAPN8 R/W SAPN10 R/W SAPN9 R/W SAPN8 R/W Offset D5h - EAPNL ........................................................................ Default value = 8'h00 EAPN7 R/W EAPN6 R/W EAPN5 R/W EAPN4 R/W EAPN3 R/W EAPN2 R/W EAPN1 R/W EAPN0 R/W (c)2007 GenesysLogic, Inc. - All rights reserved. Page 32 GL860A USB 2.0 UVC Camera Controller Offset D6h - SENINT ..................................................................... Default value = 8'h00 --7-1 RESERVED 0 EOFINT ----EOF (end of frame) Indicate EOF --------EOFINT R/W1C Offset D7h - SENINT_EN ................................................................. Default value = 8'h00 --7-1 RESERVED 0 EOFINT_EN --0 1 Disable EOFINT Enable EOFINT ----------EOFINT_EN R/W1C Offset D8h - SUB_SAMP ................................................................ Default value = 8'h00 ----PSH_MODE PSH_MODE PCLK_CNT1 PCLK_CNT0 SUB_SAMP4 SUB_SAMP2 R/W R/W R/W R/W R/W R/W 6-7 RESERVED - 5-4 PSH_MODE[1:0] "2" SEN2FF_PSH will separate 2 SEN_CLK60 "1" SEN2FF_PSH will separate 1 SEN_CLK60 "0" SEN2FF_PSH will continue 3-2 PCLK_CNT[1:0] 00 Incoming sensor data rate is the same as MCLK 01 Incoming sensor data rate is 1/2 times of MCLK 10 Incoming sensor data rate is 1/3 times of MCLK 11 Incoming sensor data rate is 1/4 times of MCLK 1 SUB_SAMP4 0 Unchanged 1 Frame size will reduce to 1/16. Pixel number which are sampled on horizontal and vertical direction separately reduce to 1/4 times. For example, a 640x480 image will be 160x120 if this bit is set. 0 SUB_SAMP2 0 Unchanged 1 Frame size will reduce to 1/4. Pixel number which are sampled on horizontal and vertical direction separately reduce to 1/2 times. For example, a 320x240 image will be 160x120 if this bit is set. (c)2007 GenesysLogic, Inc. - All rights reserved. Page 33 GL860A USB 2.0 UVC Camera Controller CHAPTER 5 FUNCTIONAL DESCRIPTION 5.1 Function Block CCD/CMOS Sensor I/F TXFIFO PIE USB 2.0 PHY CPU 8052 Figure 5.1 - Block Diagram CCD Module/CMOS Sensor Interface GL860A can link with popular CMOS sensor on market for PC camera application. GL860A can be configured by different sensor requirement. If sensor is acting as master, GL860A can accept HSYNC/VSYNC from sensor. If GL860A is configured as a master HSYNC/VSYNC will be provided by GL860A to sensor. GL860A keep the most flexibility to fit most of the sensors. The detail of configuration needs to refer to GL860A Application Note. For most sensors no matter of YUV format or RGB format, they can be easily transferred image data to PC by GL860A. TXFIFO GL860A build in 6K byte internal buffer for USB high bandwidth application. This 6K internal buffer can be used as transmitted buffer of isochronous pipe or bulk pipe. In USB specification, the highest bandwidth of isochronous pipe is 24M byte/second, that can be easily derived to maximum frame rate depending on configuration. For example, frame rate can be easily achieved to 30 frames per second if image size is 640 x 480 if raw data output and sensor clock is 15M. PIE PIE handles the USB protocol defined in chapter 8 of USB specification Revision 2.0. It co-works with CPU to play the role of the chip's kernel. The main functions of PIE include the state machine of USB protocol flow, CRC check, PID error check, and timeout check. Unlike USB1.1, bit stuffing/de-stuffing is implemented in UTMI, not in PIE. USB 2.0 PHY (UTMI ) UTMI handles the low level USB protocol and signaling. It's designed based on the Intel's UTMI specification 1.01. The major functions of UTMI logic are to handle the data and clock recovery, NRZI encoding/decoding, Bit stuffing /de-stuffing, supporting USB2.0 test modes, and serial/parallel conversion. CPU CPU is the micro-processor unit of GL860A. It is an 8-bit 8052 processor with 8K ROM and 256 bytes RAM. It operates at 15Mhz clock to decode the USB command issued from host and then prepares the data to respond to the host. In addition, C can handle GPIO (general purpose I/O) settings and reading content of EEPROM to support high flexibility for customers of different configurations of chip. These configurations include self/bus power mode setting, individual/gang mode setting, downstream port number setting, device removable/non-removable setting, and PID/VID setting. (c)2007 GenesysLogic, Inc. - All rights reserved. Page 34 GL860A USB 2.0 UVC Camera Controller 5.2 Operation Mode For customized firmware, flash memory can use as external program memory of CPU. This is for customer to develop their firmware. This is only available for 100-pin package type. 5.2.1 with Flash Memory Only available in 100-pin QFP package Force EXTCPU = 0 GPIO9 pull down GPIO13/GPIO14 used as serial bus to configure sensor 5.2.2 without Flash Memory If 100 pin, set EXTCPU = 0 GPIO9 pull down GPIO13/GPIO14 are used as serial bus to configure sensor (c)2007 GenesysLogic, Inc. - All rights reserved. Page 35 GL860A USB 2.0 UVC Camera Controller CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Maximum Ratings Table 6.1 - Maximum Ratings Symbol VIN TA FOSC 3.3V Input Voltage Ambient Temperature under bias Frequency Parameter Min. 3.0 0 Max. 3.6 +100 12 MHz 500ppm Unit V o C 6.2 DC Characteristics Table 6.2 - DC Characteristics Except USB Signals Symbol PD VDD VIL VIH VTLH VTHL VOL VOH IOLK RDN RUP Power Dissipation Power Supply Voltage LOW level input voltage HIGH level input voltage LOW to HIGH threshold voltage HIGH to LOW threshold voltage LOW level output voltage when IOL=8mA HIGH level output voltage when IOH=8mA Leakage current for pads with internal pull up or pull down resistor Pad internal pull down resister Pad internal pull up resister Parameter Min. 3 2.0 1.36 1.36 2.4 Typ. 3.3 1.48 1.48 Max. 3.6 0.9 1.62 1.62 0.4 Unit mA V V V V V V V A (c)2007 GenesysLogic, Inc. - All rights reserved. Page 36 GL860A USB 2.0 UVC Camera Controller CHAPTER 7 PACKAGE DIMENSION Figure 7.1 - GL860A 48 Pin LQFP Package (c)2007 GenesysLogic, Inc. - All rights reserved. Page 37 GL860A USB 2.0 UVC Camera Controller Internal No. Green Package Code No. Date Code Lot Code Figure 7.2 - GL860A 48 Pin LQFN Package (c)2007 GenesysLogic, Inc. - All rights reserved. Page 38 GL860A USB 2.0 UVC Camera Controller Internal No. Green Package Code No. Date Code Lot Code Figure 7.3 - GL860A 46 Pin LQFN Package (c)2007 GenesysLogic, Inc. - All rights reserved. Page 39 GL860A USB 2.0 UVC Camera Controller CHAPTER 8 ORDERING INFORMATION Table 8.1 - Ordering Information Part Number GL860A-MNGXX GL860A-PNGXX GL860A-PMGXX Package 48-pin LQFP 48-pin LQFN 46-pin LQFN Green Green Package Green Package Green Package Version XX XX XX Status Available Available Available (c)2007 GenesysLogic, Inc. - All rights reserved. Page 40 GL860A USB 2.0 UVC Camera Controller Appendix A. Application circuit The schematic below represents a very basic example to the controller and is subject to variations depending on application intentions. (c)2007 GenesysLogic, Inc. - All rights reserved. Page 41 GL860A USB 2.0 UVC Camera Controller (c)2007 GenesysLogic, Inc. - All rights reserved. Page 42 |
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